NOVEL PARALLEL ARCHITECTURES FOR SHORT-TIME FOURIER-TRANSFORM

被引：44
|
作者：
LIU, KJR [1 ]
机构：
[1] UNIV MARYLAND,INST SYST RES,COLL PK,MD 20742
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1993年 / 40卷 / 12期
基金：
美国国家科学基金会;
关键词：
D O I：
10.1109/82.260243
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Novel parallel architectures for short-time Fourier transform based on adaptive time-recursive processing is proposed for efficient VLSI implementation. Only N-1 multipliers and N+1 adders are required. The proposed approach can be easily extended to multi-dimensional cases without the transpose operation. Various properties of the proposed architectures are also presented.
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页码：786 / 790
页数：5
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