Communication-oriented performance optimisation during code generation from Simulink models

被引:2
|
作者
Yan, Rongjie [1 ]
Yu, Min [2 ]
Huang, Kai [2 ]
Zhang, Xiaomeng [2 ]
机构
[1] Chinese Acad Sci, Inst Software, State Key Lab Comp Sci, Beijing 100190, Peoples R China
[2] Zhejiang Univ, Inst VLSI Design, Hangzhou 310013, Zhejiang, Peoples R China
基金
美国国家科学基金会;
关键词
multi-threaded code generation; communication pipeline; cyclic topology; scheduling strategy;
D O I
10.1504/IJES.2014.063809
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Increasing complexity of embedded systems brings a big challenge for designers to satisfy requirements for both high-performance and programmability. Automatic multi-threaded code generation facilitates MPSoC-based programming greatly. Apart from the savings on programming effort, system performance is also an important issue to be considered during code generation process. As thread communication is quite frequent in multi-threaded code, system performance will be improved by reducing communication cost. Communication pipeline technique applies distributed memory server for parallel execution between message passing and functional tasks, to reduce the cost caused by communication between different processors. The technique can be applied directly to communicating threads in acyclic topologies. To maximise its application, we also provide a solution to apply the technique to cyclic topologies with allocable delay units. Furthermore, we introduce a scheduling strategy for local threads to improve communication efficiency and processor usage. Experimental results demonstrate the performance improvements with the proposed techniques.
引用
收藏
页码:124 / 134
页数:11
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