A STEADY-STATE VDMOS TRANSISTOR MODEL

An analytical model is proposed in order to explain the dc VDMOS transistor performance. It accounts for the device linear region, and the quasi-saturation effect is included in the formulation by considering the carrier velocity saturation at high electric field values. Electric field and majority-carrier distributions can be deduced from the model which agree with the results obtained from two-dimensional simulations. This formulation predicts a majority-carrier excess inside the epilayer even before the carrier velocity saturation is achieved. Interdigitated VDMOS transistors have been fabricated and two-dimensional simulations have been carried out in order to check the output characteristics against the proposed model.