A 17-NS 4-MB CMOS DRAM

被引：6
|
作者：
NAGAI, T
NUMATA, K
OGIHARA, M
SHIMIZU, M
IMAI, K
HARA, T
YOSHIDA, M
SAITO, Y
ASAO, Y
SAWADA, S
FUJII, S
机构：
[1] TOSHIBA CO LTD,ULSI RES CTR,KAWASAKI 210,JAPAN
[2] TOSHIBA CO LTD,DEPT MEMORY IC ENGN,KAWASAKI 210,JAPAN
[3] TOSHIBA CO LTD,TOSHIBA RES & DEV CTR,KAWASAKI 210,JAPAN
[4] TOSHIBA MICROELECTRON CORP,SAIWAI KU,KAWASAKI 210,JAPAN
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 11期
关键词：
D O I：
10.1109/4.98969
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 17-ns nonaddress-multiplexed 4-Mb DRAM fabricated with a pure CMOS process is presented. The RAM incorporates a direct bit-line sensing technique with a two-stage current-mirror readout amplifier. The high sensitivity of a current-mirror amplifier enables a small bit-line signal to be amplified without waiting for the start of the bit-line latch action. The chip measures 4.76 x 11.06 mm2 with x 1/x 4 organization.
引用
收藏
页码：1538 / 1543
页数：6
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