Improving the Performance of a Scalable Encryption Algorithm (SEA) using FPGA

The present symmetric encryption algorithms result from a Tradeoff between implementation cost and resulting performances. SEA is a scalable encryption algorithm targeted for small embedded applications. It was initially designed for software implementations in controllers, smart cards, or processors. In this Paper we proposed a system that investigates its performances in recent field-programmable gate array (FPGA) devices. The proposed system is applicable where there are limited processing resources and throughput requirements. For this purpose, we propose low-cost encryption routines (i.e. with small code size and memory) targeted for processors with a limited instruction set (i.e. AND, OR, XOR gates, word rotation and modular addition). The proposed design is parametric in the text, key and processor size, provably secure against linear or differential cryptanalysis, allows efficient combination of encryption/decryption and on-the-fly" key derivation. Beyond its low cost performances, a significant advantage of the proposed architecture is its full flexibility for any parameter of the scalable encryption algorithm, taking advantage of generic VHDL coding.