TRENDS AND LIMITS IN MONOLITHIC INTEGRATION BY INCREASING THE DIE AREA

Silicon technology continues to increase the scale of integration by simultaneously miniaturizing the circuit elements, and growing the die. Fundamental physical laws place limits on miniaturization. Here we consider the limits on growing the die area, and argue that they are essentially economic. The discussion is in terms of a simple system-cost model. At a given defect density, the optimum die area is determined by the balance between two opposing forces: reducing the assembly cost, achieved by growing the die to bring interconnects on chip; and reducing the scrapping cost, achieved by shrinking the die to reduce the amount of processed Si lost every time defects occur. Our model accurately reproduces past trends, and predicts the die area which minimizes the cost of a system of given complexity. Extrapolation of present trends indicates that the economic advantage of growing the die may be exhausted at die areas of approximately 8-20 cm2. Dice with such an area may be encountered by the year 2010, when fundamental limits on miniaturization are also anticipated. However, these conclusions may be mitigated by new fault-tolerant architectures, or in systems where performance is paramount.