VLSI LOGIC AND FAULT SIMULATION ON GENERAL-PURPOSE PARALLEL COMPUTERS

With the advances in very large scale integration (VLSI) technology there is an increased need for simulation tools that are able to handle large designs efficiently. In this research, we consider the use of general-purpose multiprocessors for various simulation tasks. The aims of our work are: 1) to define a general framework for the parallel simulation of digital systems; and 2) to develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. In our approach, we partition the design to be simulated, rather than simulating a copy of the complete circuit on each processor with a different set of inputs. This paper first reviews previous work and identifies central issues. Then a high-level process model of parallel simulation is presented to clarify essential design choices. We introduce algorithms for parallel logic and fault simulation of synchronous gate-level designs. The algorithms are based on a new partitioning approach that reduces the number of necessary synchronizations between processors. A simple performance model characterizes the dependence on some crucial parameters. Experimental results for some large benchmarks are given, using prototype implementations for both message passing and shared memory machines.