Shuffled Frog Leaping Algorithm for Hardware/Software Partitioning

Reconfigurable system on chip is well known for its flexibility for high performance embedded systems. The hardware/software (HW/SW) partitioning is the most important phase during the design of reconfigurable system on chip. A great many different algorithms have been adopted for solving the hardware/software partitioning problem. Shuffled Frog Leaping Algorithm (SFLA) is popular for its simple concepts, little parameter adjustment, high calculation speed, strong global search optimization capability and easy execution. In this paper, we apply the SFLA algorithm to solving hardware/software partitioning problem on reconfigurable system on chip with coarsegrained. The experimental results show that the SFLA algorithm can reduce the time cost by 45.54% on average with three different area constrain, compared with greedy algorithm. The time cost of SFLA algorithm are also reduced by 23.57% and 9.99% on average with simulated annealing algorithm (SA) and combined algorithm with greedy and simulated annealing algorithm (GSA). When area constrain is a half of area cost which all tasks are implemented by hardware will be taken, SFLA algorithm can reduce the time cost by 51.30%, 21.04% and 11.61% on average, compared with that of Greedy algorithm, SA, and GSA, respectively.