共 50 条
- [2] Automatic generation of assertions for formal verification of PowerPC™ microprocessor arrays using symbolic trajectory evaluation [J]. 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 534 - 537
- [4] Symbolic simulation of microprocessor models using type classes in Haskell [J]. CORRECT HARDWARE DESIGN AND VERIFICATION METHODS, 1999, 1703 : 346 - 349
- [5] Symbolic reliability evaluation of a software with network structure [J]. OPSEARCH, 2004, 41 (3) : 165 - 177
- [7] MICROPROCESSOR DEVICE RELIABILITY [J]. MICROELECTRONICS AND RELIABILITY, 1978, 17 (03): : 379 - 385