SPECIFICATION AND SYNTHESIS OF COMMUNICATING FINITE-STATE MACHINES

A general VHDL model for communicating finite state machines is introduced. This controller model should retain the natural partitioning of the behaviour imposed by the designer and allows him to describe his controller in blocks of manageable size. This leads to the declaration of well defined FSMs communicating with few signals. A study of the representation power of the proposed model, described in VHDL, shows that it covers all interacting FSMs schemes. A synthesis method and a tool capable of synthesizing distributed, hierarchical and parallel controllers from VHDL specifications is provided. An example illustrating our approach is given.