This paper describes an engineering workstation environment that supports student laboratories in computer architecture. The backbone of this environment is a digital simulator that gives each first-term architecture student the necessary power to produce their own working (simulated) computer. These 8-bit computers are of 1000-2000 gate-equivalent complexity, plus the ram and rom chips. These computers support a register file, a stack for function linking, and a single-level interrupt system. The addressing modes included are: immediate, register direct, memory direct, and register indirect. The computers are constructed in an hierarchical manner and the dynamic screen-graphics presentation of the completed computers allow viewing the levels of the hierarchy, such as (at the highest level): the ALU, control, memory, I/O, and allow, as well, zooming in to intermediate levels and finally to the lowest levels to see the values of bits stored in single register cells and the outputs of individual gates. Supplemental workstation tools include: minimal-covering equation generator, reduction of arbitrary Boolean functions to sum-of-products form, generation of the netlist form of encapsulated modules from equation form, automatic generation of a test fixture, in netlist form, for validating components generated automatically from describing equations, and an assembler for the simulated microcomputer. Second term projects reach 6000 gate-equivalent complexity levels in implementing associative memories, asynchronous and bus-communicating multiprocessors, pipelining, and parallel processors with 16 processing elements.
