THE EFFECT OF SIPOS ON THE PERFORMANCE OF LATERAL INSULATED GATE BIPOLAR-TRANSISTORS

被引：0

作者：

CHOW, TP ^{[1
]}

PATTANAYAK, DN ^{[1
]}

BALIGA, BJ ^{[1
]}

ADLER, MS ^{[1
]}

机构：

[1] GE,CORP RES & DEV,SCHENECTADY,NY 12301

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 1987年 / 34卷 / 11期

关键词：

D O I：

10.1109/T-ED.1987.23253

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：2359 / 2359

页数：1

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