ASSOCIATIVE MASSIVELY PARALLEL COMPUTERS

Massively Parallel Computers (MPC's) are playing an important role in providing powerful computing environments for a wide variety of computationally intensive applications requiring up to Tera (1E12) operations per second (TOPS) performance levels. MPC's must address the engineering issues of size, weight, and power dissipation, combined with the equally important factors of cost, reliability, maintenance, and environmental restrictions. While first-generation MPC's have already been shown to successfully address a broad range of applications, many lack a clear path to achieving the degree of scalability required for TOPS performance, and most have ignored the engineering issues. In contrast, second-generation MPC's aim to achieve a cost-effective solution to such problems with integrated end-to-end applications-oriented computational systems. Associative Processing architectures are promising candidates for second-generation MPC's, offering the potential for applications flexibility, while addressing the issues of scalability and engineering viability. This paper outlines the principle of operation of associative processors, and briefly reviews their development. It then goes on to explore the Associative String Processor (ASP) architecture, as a representative case study in the development of a second-generation MPC.