A BOOTSTRAPPED BIPOLAR CMOS (B(2)CMOS) GATE FOR LOW-VOLTAGE APPLICATIONS

被引：11

作者：

EMBABI, SHK ^{[1
]}

BELLAOUAR, A ^{[1
]}

ISLAM, K ^{[1
]}

机构：

[1] CDTA,MICROELECTR LAB,ALGIERS 16075,ALGERIA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1995年 / 30卷 / 01期

关键词：

D O I：

10.1109/4.350195

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports on a BiCMOS logic gate which combines bootstrapping and transient saturation techniques to achieve full swing operation down to 1.1 V supply voltage. The proposed B(2)CMOS uses a conventional (noncomplementary) BiCMOS process. HSPICE simulations have been used to compare the B(2)CMOS to CMOS, BiNMOS, and BS-BiCMOS CMOS for sub-0.5 mu m BiCMOS technologies. Simulation results have shown that the B(2)CMOS gate outperforms CMOS, BiNMOS, and BS-BiCMOS gates at 3 V and below. The crossover capacitance/fanout of the B(2)CMOS gate is 100 fF (i.e., fanout of 4) at 1.5 V. The delay-to-load sensitivity of the B(2)CMOS is 220 ps/pF (8 ps/fanout) which is one order of magnitude smaller than that of CMOS at 1.5 V.

引用

页码：47 / 53

页数：7

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