A SYSTEM ARCHITECTURE FOR MULTILEVEL DECISION-FEEDBACK EQUALIZATION

被引：2
|
作者：
KENNEY, JG
机构：
[1] Department of ECE, Oregon State University, Corvallis
来源：
IEEE TRANSACTIONS ON MAGNETICS | 1994年 / 30卷 / 06期
关键词：
D O I：
10.1109/20.334040
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
System issues such as clock recovery, automatic gain control and determination of the filter coefficients for both the forward and backward equalizers are examined for multi-level decision feedback equalization (MDFE). A software implementation on 2/3(1,7) RLL coded data stored at a bit density of 1.67 PW50 and retrieved by an MR head demonstrate the implementation of a channel based on MDFE.
引用
收藏
页码：4218 / 4220
页数：3
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