HIGH-SPEED SENSING TECHNIQUES FOR ULTRAHIGH-SPEED SRAMS

Two high-speed sensing techniques suitable for ultrahigh-speed SRAM's are proposed. These techniques can reduce a 64-kb SRAM access time to 71 approximately 89% of that of conventional high-speed bipolar SRAM's. The techniques use a small CMOS memory cell instead of the bipolar memory cell that has often been used in conventional bipolar SRAM's for cache and control memories of mainframe computers. Therefore, the memory cell size can also be reduced to 26 approximately 43% of conventional cells. A 64-kb SRAM with one of the sensing techniques is fabricated using 0.5-mu-m BiCMOS technology and achieves a 1.5-ns access time with a 78-mu-m2 memory cell size. The techniques are especially useful in the development of both ultrahigh-speed and high-density SRAM's, which have been used as cache and control memories of mainframe computers.