Testing and Diagnosis Methodologies for Embedded Content Addressable Memories

被引:0
|
作者
Jin-Fu Li
Ruey-Shing Tzeng
Cheng-Wen Wu
机构
[1] National Central University,Department of Electrical Engineering
[2] National Tsing Hua University,Laboratory for Reliable Computing (LARC), Department of Electrical Engineering
来源
关键词
BIST; CAM; march test algorithm; memory diagnostics; memory testing;
D O I
暂无
中图分类号
学科分类号
摘要
Embedded content addressable memories (CAMs) are important components in many system chips where most CAMs are customized and have wide words. This poses challenges on testing and diagnosis. In this paper two efficient March-like test algorithms are proposed first. In addition to typical RAM faults, they also cover CAM-specific comparison faults. The first algorithm requires 9N Read/Write operations and 2(N + W) Compare operations to cover comparison and RAM faults (but does not fully cover the intra-word coupling faults), for an N × W-bit CAM. The second algorithm uses 3N log2W Write and 2W log2W Compare operations to cover the remaining intra-word coupling faults. Compared with the previous algorithms, the proposed algorithms have higher fault coverage and lower time complexity. Moreover, it can test the CAM even when its comparison result is observed only by the Hit output or the priority encoder output. We also present the algorithms that can locate the cells with comparison faults. Finally, a CAM BIST design is briefly described.
引用
收藏
页码:207 / 215
页数:8
相关论文
共 50 条
  • [1] Testing and diagnosis methodologies for embedded content addressable memories
    Li, JF
    Tzeng, RS
    Wu, CW
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 2003, 19 (02): : 207 - 215
  • [2] METHODOLOGIES FOR TESTING EMBEDDED CONTENT ADDRESSABLE MEMORIES
    MAZUMDER, P
    PATEL, JH
    FUCHS, WK
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (01) : 11 - 20
  • [3] Testing and diagnosing embedded content addressable memories
    Li, JF
    Tzeng, RS
    Wu, CW
    20TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2002, : 389 - 394
  • [4] Path-Delay Fault testing in Embedded Content Addressable Memories
    Manikandan, P.
    Larsen, Bjorn B.
    Aas, Einar J.
    13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, 2010, : 519 - 524
  • [5] Functional testing of content-addressable memories
    Lin, KJ
    Wu, CW
    1998 INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING - PROCEEDINGS, 1998, : 70 - 75
  • [6] Generic BIST Architecture for Testing of Content Addressable Memories
    Grigoryan, H.
    Harutyunyan, G.
    Shoukourian, S.
    Vardanian, V.
    Zorian, Y.
    2011 IEEE 17TH INTERNATIONAL ON-LINE TESTING SYMPOSIUM (IOLTS), 2011,
  • [7] Testing SRAM-based content addressable memories
    Zhao, J
    Irrinki, S
    Puri, M
    Lombardi, F
    IEEE TRANSACTIONS ON COMPUTERS, 2000, 49 (10) : 1054 - 1063
  • [8] Testing content addressable memories with physical fault models
    Ma Lin
    Yang Xu
    Zhong Shiqiang
    Chen Yunji
    JOURNAL OF SEMICONDUCTORS, 2009, 30 (08)
  • [9] Fault modeling and testing of content-addressable memories
    Al-Assadi, W.K., 1600, IEEE, Los Alamitos, CA, United States
  • [10] Modeling and testing comparison faults for ternary content addressable memories
    Li, JF
    Lin, CK
    23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 2005, : 60 - 65