Analog and Mixed-Signal Extensions to VHDL

Hardware description languages (HDL) such as VHDL are today an essential technology to support most of the steps of digital hardware design, such as simulation, synthesis, testing, and formal proof. As the IEEE 1076 standard, VHDL is committed to evolve through five years re-standardization cycles whose objective is to make the necessary language changes or extensions in response to feedbacks from users and from tool suppliers. Requirements to support analog and mixed-signal systems have been issued during the initial phases of the second VHDL re-standardization cycle. Due to the complexity of the topic, a separate IEEE working group, referenced as 1076.1, was formally formed in 1993 with the charter to provide a language proposal based on VHDL 1076 that includes these new requirements. The language design phase is now complete and a solid language architecture is defined. A formal IEEE balloting process to approve the proposal as the new IEEE Standard 1076.1 has started in August 1997 and will be completed before the end of the year. This paper presents an overview of the 1076.1 language proposal that enhances VHDL to handle systems that exhibit continuous behavior over time and over amplitude. The way it is designed, VHDL 1076.1 will support the description and the simulation of both non-conservative and conservative continuous and mixed discrete/continuous systems.