All-2D ReS2 transistors with split gates for logic circuitry

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Junyoung Kwon
Yongjun Shin
Hyeokjae Kwon
Jae Yoon Lee
Hyunik Park
Kenji Watanabe
Takashi Taniguchi
Jihyun Kim
Chul-Ho Lee
Seongil Im
Gwan-Hyoung Lee
机构
[1] Yonsei University,Department of Materials Science and Engineering
[2] Seoul National University,Department of Materials Science and Engineering
[3] Yonsei University,vdWMRC, Department of Physics
[4] Korea University,KU‐KIST Graduate School of Converging Science and Technology
[5] Korea University,Department of Chemical and Biological Engineering
[6] National Institute for Materials Science,undefined
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Two-dimensional (2D) semiconductors, such as transition metal dichalcogenides (TMDs) and black phosphorus, are the most promising channel materials for future electronics because of their unique electrical properties. Even though a number of 2D-materials-based logic devices have been demonstrated to date, most of them are a combination of more than two unit devices. If logic devices can be realized in a single channel, it would be advantageous for higher integration and functionality. In this study we report high-performance van der Waals heterostructure (vdW) ReS2 transistors with graphene electrodes on atomically flat hBN, and demonstrate a NAND gate comprising a single ReS2 transistor with split gates. Highly sensitive electrostatic doping of ReS2 enables fabrication of gate-tunable NAND logic gates, which cannot be achieved in bulk semiconductor materials because of the absence of gate tunability. The vdW heterostructure NAND gate comprising a single transistor paves a novel way to realize “all-2D” circuitry for flexible and transparent electronic applications.
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