Performance investigation of packet-based communication in 3D-memories

Recent advances in 3D fabrication have allowed the development of 3D memory over the logic die. The 3D memory presents itself as a viable solution to the memory wall problem. The 3D memory has stacked DRAM layers connected with Through Silicon Vias (TSVs). In the coming future, data-intensive applications on memory-centric network architecture will rely on packet-based communication to ensure scalability and reliable data transfers. The paper studies the performance of 3D memory that uses a packet-based communication protocol for communication between the CPU and off-chip memory. Our study provides insight into the internal flit traffic for different configurations of 3D memory when observed under the diverse memory access patterns and workload characteristics. We use CasHMC to capture the effect on performance for packet-based communication protocol and have integrated it with the gem5 simulator to study the workloads from Rodinia Benchmarks Suite. Our evaluation focuses on the following metrics- total memory bandwidth utilization, off-chip link bandwidth utilization, latency, & power consumption. We look at the performance characteristics of the 3D stacked memory, under the variation of the number of banks and vaults in the structure. Further, the effect of varying the packet size and the number of communication links on off-chip link bandwidth and latency have been studied. We further examine different off-chip link power optimization strategies. Finally, we observe the impact of varying buffer sizes on the latency at the off-chip links buffer and at the vault buffer of 3D memory. Our study provides more perspective into further developments of Data Centric Computing architectures and insight into proper flit management strategies in future memory architectures.