Modelling and Optimization of Phase Locked Loop under Constrained Channel Length and Width of MOSFETs

CMOS integrated circuits consisting of MOSFETs have tradeoffs among their performance parameters. Hence they need minimization in those tradeoffs calling for multi objective optimization to yield a circuit with enhanced characteristics. To perform simultaneous optimization of the Phase locked loop (PLL) performances using an effective multi objective optimization technique saving the designer’s time and causing the near best performance is the motivation of this work. Though the designer can optimize the circuit in the netlist level, it is less effective and a time consuming iterative process and sometimes it is next to impossible for complex and nanoscale circuits with large number of MOSFET devices and interconnects. Performance parameters like phase noise, lock time and power consumption are optimized subject to the practical design constraints using an efficient multi-objective optimization technique, infeasibility driven evolutionary algorithm (IDEA) in a real time environment. Using design parameters like the channel length and width of the MOSFETs for optimal performance, the PLL is simulated for model validation. Significantly superior performance achieved by the designed PLL is demonstrated. The phase noise, average power consumption and lock time achieved here are −126.3 dBc/Hz at 1 MHz offset frequency, 1.523 mW and 50 nS respectively.