Analysis and experimental tests of a solid-state fault current limiter

被引:0
|
作者
Alexandre Bitencourt
Cauê Nogueira
Gabriel dos Santos
D. H. N. Dias
B. W. França
F. Sass
G. G. Sotelo
机构
[1] Universidade Federal Fluminense,
来源
Electrical Engineering | 2023年 / 105卷
关键词
Solid state; Fault current limiter; Power electronics; Controller; Fault detection algorithm control;
D O I
暂无
中图分类号
学科分类号
摘要
The increase in distribution power demand and distributed generation may lead to a rise in power substation fault current levels. One possible solution to this problem is the use of a solid-state fault current limiter (SS-FCL). In this context, this paper proposes the concept of a bridge-type solid-state device switching an air-core reactor as an SS-FCL topology. The overvoltage protection system details are presented, along with an explanation of the fault detection algorithm control's principle. An experimental setup is designed to evaluate various events in addition to the short-circuit, such as load-steps, harmonic loads, motor startups, and transformer’s inrush. Fault current is detected within one millisecond, with a total reduction of 42%. The overvoltage protection system clamped the peak voltage across the semiconductor switch and kept the dV/dt below the maximum stipulated. The load input tests showed a proper limiting operation and provided that the device is within the parameterization range.
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页码:3219 / 3228
页数:9
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