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- [1] An efficient technique for leakage current estimation in sub 65nm scaled CMOS circuits based on loading effect 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS: TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, 2007, : 583 - +
- [2] Simulation-Based Understanding of "Charge-Sharing Phenomenon" Induced by Heavy-Ion Incident on a 65nm Bulk CMOS Memory Circuit IEICE TRANSACTIONS ON ELECTRONICS, 2022, E105C (01): : 47 - 50
- [3] Simulation Study of Single Event Effect for Different N-Well and Deep-N-Well Doping in 65nm Triple-Well CMOS Devices 2012 INTERNATIONAL CONFERENCE ON OPTOELECTRONICS AND MICROELECTRONICS (ICOM), 2012, : 505 - 509