Adaptive design and implementation of automatic modulation recognition accelerator

Automatic modulation recognition-oriented Deep Neural Networks (ADNNs) have achieved higher recognition accuracy than traditional methods with less labor overhead. However, their high computation complexity usually far exceeds the computation capacity of communication devices built on Field Programmable Gate Array (FPGA) platform. When solving the problem of insufficient resources, the complete operation of FPGA-based accelerator can be achieved by dividing the calculation into several parts and calculating them separately, but this will cause unaccepTable latency. In this backdrop, we develop a new ADNN model, named VT-CNN2+, to promote the recognition accuracy. Then, after stating the resources and latency problems for implementing VT-CNN2+ on the FPGA platform, an adaptive hardware accelerator is put forward. To implement the accelerator, Area folding is introduced to optimize resources consumption. Moreover, Literacy Optimization, Parallelism Optimization, Inter-layer Cascading, Temporary Cache and Data Loading Optimization are adopted to reduce latency. Afterwords, the two components in our accelerator are detailed, i.e., Once-designed module and Re-designed module. Finally, to evaluate the performance and adaptivity of our accelerator, a series of experiments are conducted on two different FPGA platforms, i.e., AX7350 and ZedBoard. Results show that our accelerator can successfully adapt to different FPGA platforms and it can remarkably reduce the processing latency. Moreover, our accelerator’s processing speed of 0.066249s per single data sample with much lower energy consumption is one order of magnitude faster than desktop-level Central Processing Units (CPUs), two orders of magnitude faster than embedded CPUs. © The Author(s), under exclusive licence to Springer-Verlag GmbH Germany, part of Springer Nature 2024.