A 1.8-V 0.7 ppm/°C high order temperature-compensated CMOS current reference

A high order curvature compensation technique for current reference generator which exploits the I–V characteristic of MOS to achieve ISC (Tm) (m ≥ 2) is described. ISC (Tm) is a self-compensated current which corrects its negative three-order TC (Temperature Coefficient) and linear TC by itself. Then, I (T2) is achieved also by exploiting the I–V characteristic of MOS, for correcting the other negative high order parts of ISC (Tm). This circuit operates on a 1.8 V power supply and is compatible with a standard n-well 0.5-μm digital CMOS process. The circuit realizes a temperature coefficient of 0.7 ppm/°C, a deviation of the simulated output current of 0.011% from −20°C to + 150°C and 97.5 dB PSRR through HSPICE simulation.