Design and optimization of junctionless-based devices with noise reduction for ultra-high frequency applications

This paper offers the study of the noise performance of four devices namely junctionless dual-gate FET (JL-DGFET), junctionless nanowire FET (JL-NWFET), charge-plasma based dopingless dual-gate FET (DL-DGFET) and dopingless nanowire FET (DL-NWFET). This work examines the maximum Noise-Figure (NFmax.), Auto-correlation factor (< V1·V1* >)/(< V2·V2* >), cross-correlation factor (< V1·V2* >), and output impedance (real Zo). To understand the performance of devices, analog characteristics of all four devices and effect on these characteristics with the variations of different device structure parameters are analyzed and compared. Internal physics of device is understood by device design parameters such as electric field, channel potential, carrier mobility and carrier concentration. It is observed from the simulated results that JL-DGFET has better noise performance, highest ION/IOFF current ratio than other devices.