Low temperature wafer level conformal polymer dielectric spray coating for through silicon vias with 2:1 aspect ratio

This paper presents a detailed study to perform low temperature spray coating polymer dielectric process with good conformal deposition on aspect ratio features (2:1) through silicon via (TSV) CMOS image sensor (CIS) wafer-level-packaging. In this study, one kind of phenolic aldehyde polymer is deposited on the sidewall of though silicon via by spray coating process. Individual conditions that affect the weak-point of polymer dielectric on the TSV sidewall and step coverage such as nitrogen gas pressure, polymer so lution flow rate and temperature are investigated. The optimal condition is used to deposit into TSVs by spray coating process. The results turn to give excellent step coverage and satisfied weak-point (>2 µm) on the sidewall of though silicon via with the diameter of 65 µm and depth of 130 µm.