A parallel pattern for iterative stencil + reduce

被引:0
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作者
M. Aldinucci
M. Danelutto
M. Drocco
P. Kilpatrick
C. Misale
G. Peretti Pezzi
M. Torquati
机构
[1] University of Pisa,Department of Computer Science
[2] University of Turin,Department of Computer Science
[3] Queen’s University Belfast,Department of Computer Science
[4] Swiss National Supercomputing Centre,undefined
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关键词
Parallel patterns; OpenCL; GPUs; Heterogeneous multi-cores;
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学科分类号
摘要
We advocate the Loop-of-stencil-reduce pattern as a means of simplifying the implementation of data-parallel programs on heterogeneous multi-core platforms. Loop-of-stencil-reduce is general enough to subsume map, reduce, map-reduce, stencil, stencil-reduce, and, crucially, their usage in a loop in both data-parallel and streaming applications, or a combination of both. The pattern makes it possible to deploy a single stencil computation kernel on different GPUs. We discuss the implementation of Loop-of-stencil-reduce in FastFlow, a framework for the implementation of applications based on the parallel patterns. Experiments are presented to illustrate the use of Loop-of-stencil-reduce in developing data-parallel kernels running on heterogeneous systems.
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页码:5690 / 5705
页数:15
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