A hot-module-aware mapping approach in network-on-chip

In this research, a hot module location-aware heuristic mapping algorithm for placement of hot modules is proposed, which aims to prevent the negative effects of tasks on the performance metrics of 2D network-on-chip. This method uses modular systematic and exact search optimization techniques to obtain an optimal solution to the mapping problem. Significant performance degradation and unfair allocation of system resources can occur with one or more hot modules on the network on the wormhole-base network system. By defining a specific access system for hot modules, the proposed approach optimizes system latency and throughput and minimizes energy consumption under bandwidth limitations. The efficiency and effectiveness of the proposed approach have been compared in simulation environments and similar traffic conditions. Saving energy consumption of the proposed approach compared to the equivalent algorithms for embedded systems, up to 81.69% less delay and 68% energy saving have been obtained.