Frequency Spectrum Based Low-Area Low-Power Parallel FIR Filter Design

被引:0
|
作者
Jin-Gyun Chung
Keshab K. Parhi
机构
[1] Chonbuk National University,Division of Electronic and Information Engineering
[2] University of Minnesota,Department of Electrical and Computer Engineering
关键词
parallel FIR filter; quantization; fast FIR algorithm; canonic signed digit;
D O I
暂无
中图分类号
学科分类号
摘要
Parallel (or block) FIR digital filters can be used either for high-speed or low-power (with reduced supply voltage) applications. Traditional parallel filter implementations cause linear increase in the hardware cost with respect to the block size. Recently, an efficient parallel FIR filter implementation technique requiring a less-than linear increase in the hardware cost was proposed. This paper makes two contributions. First, the filter spectrum characteristics are exploited to select the best fast filter structures. Second, a novel block filter quantization algorithm is introduced. Using filter benchmarks, it is shown that the use of the appropriate fast FIR filter structures and the proposed quantization scheme can result in reduction in the number of binary adders up to 20%.
引用
收藏
相关论文
共 50 条
  • [1] Frequency spectrum based low-area low-power parallel FIR filter design
    Chung, J.-G. (jgchung@moak.chonbuk.ac.kr), 1600, Hindawi Publishing Corporation (2002):
  • [2] Frequency spectrum based low-area low-power parallel FIR filter design
    Chung, JG
    Parhi, KK
    EURASIP JOURNAL ON APPLIED SIGNAL PROCESSING, 2002, 2002 (09) : 944 - 953
  • [3] Low-area/power parallel FIR digital filter implementations
    Parker, DA
    Parhi, KK
    JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, 1997, 17 (01): : 75 - 92
  • [4] Low-area/power parallel FIR digital filter implementations
    Theseus Logic, Inc, St. Paul, United States
    J VLSI Signal Process, 1 (75-92):
  • [5] Low-Area/Power Parallel FIR Digital Filter Implementations
    David A. Parker
    Keshab K. Parhi
    Journal of VLSI signal processing systems for signal, image and video technology, 1997, 17 : 75 - 92
  • [6] Low-Power, High-Throughput, and Low-Area Adaptive FIR Filter Based on Distributed Arithmetic
    Park, Sang Yoon
    Meher, Pramod Kumar
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2013, 60 (06) : 346 - 350
  • [7] Design of low-power low-area asynchronous iterative multiplier
    You, Heng
    Hei, Yong
    Yuan, Jia
    Tang, Weidi
    Bai, Xu
    Qiao, Shushan
    IEICE ELECTRONICS EXPRESS, 2019, 16 (11)
  • [8] A low-area, low-power programmable frequency multiplier for DLL based clock synthesizers
    Faisal, Md Ibrahim
    Bayoumi, Magdy A.
    PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10, 2008, : 1460 - 1463
  • [9] Design of Low-Power Low-Area Tunable Active RC Filters
    Rasekh, Amirhossein
    Bakhtiar, M. Sharif
    IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2018, 65 (01) : 6 - 10
  • [10] Design and implementation of low-area and low-power AES encryption hardware core
    Hamalainen, Panu
    Alho, Tirno
    Hannikainen, Marko
    Hamalainen, Tirno D.
    DSD 2006: 9TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, PROCEEDINGS, 2006, : 577 - +