A mutated addition–subtraction unit to reduce the complexity of FFT

Butterfly operation is the most computationally intensive stage in Fast Fourier Transform (FFT) systems. Adders and multipliers are the basic building blocks of a traditional butterfly unit. As a result, implementing a low-power butterfly unit in a low-power FFT architecture revolves around the arithmetic circuits. Therefore, in this work, the addition and subtraction operations are mutated together as a single operation by eliminating the common expressions between the two, which results in the utilization of a less number of transistors. The simulated results exhibit the progressive improvement in performance parameters which includes area, power, and delay. The study on the effect of variation in supply voltage and the load capacitance on the computation of FFT for the given block size achieves low power consumption. The mutated unit is extended to 8 bit, 12 bit and 16 bit of data width, in a butterfly computation unit which decreases the accommodation of MOS transistor in each unit. The 8 bit unit saves 16 clock cycles when executed with a single clock. The Monte Carlo simulation is carried out with normal distribution for 100 runs, to report the variations in process parameters is lesser in value for the targeted design. The complexity of FFT structure is considerably reduced by 43% in the proposed computation unit in comparison with the existing literature for the computation of the butterfly structure of FFT by employing Gate Diffused Inputs technique.