Deep Insight into Raised Buried Oxide SOI-Fe TFET and It’s Analog/RF and Linearity Performance Parameters

Here, the proposed device is a negative capacitance based ferroelectric gate stack, raised buried oxide pocket doped SOI TFET (RBOX-SOI-Fe TFET). The architecture of the device is carefully designed with proper optimization of the pocket and ferroelectric thickness to boost the on-state current, on–off current ratio, and to improve subthreshold swing. At, first the polarization versus electric field curve of the proposed device is studied. Next, the DC and the analog/RF, linearity performance analysis are illustrated. The various analog/RF performance parameters like gate-to-source capacitance (Cgs-1.7 × 10−16 F/µm), gate-to-drain capacitance (Cgd-2.3 × 10−17 F/µm), total capacitance (Cgg-1.96 × 10−16 F/µm), transconductance (7.35 × 10−3 S/µm), output conductance, corner frequency (7.1 × 1013 Hz), the gain bandwidth product (1.2 × 1013 Hz), transit time (1.4 × 10−15 s), transistor frequency product (3.1 × 1015 Hz/V), and intrinsic gain (6.91 × 103) have been investigated. The proposed device parameters have been compared with the existing devices in literature and RBOX-SOI-Fe TFET evinces an improved result in terms of both DC and Analog/RF parameters. Device simulations have been performed by Sentaurus TCAD 2D-simulator.