A New Low Voltage Current Mode Analog Multiplier/Divider Circuit Based on FGMOS Translinear Loop

This paper presents a novel low voltage current mode analog multiplier/divider. The proposed circuit comprises of a floating gate MOSFET (FGMOS) translinear loop and a squarer to obtain the required product of two currents. Translinear loop offer the advantage of insensitivity to process and temperature variation, and FGMOS provides low power operation and circuit simplicity. To evaluate the circuit operation, simulations have been done using Ltspice software in 180 nm CMOS technology. The proposed circuit operates at 1 V, while consuming 133.27 µW power at the quiescent point and observes a linearity error less than 0.25%. Total harmonic distortion (THD) of the proposed circuit for different frequencies has been analyzed, and it has been observed that the maximum THD is 2.5% for the entire range of operation. The linearity of the proposed circuit has been analyzed by calculating intermodulation product. Proper functioning and usability of the proposed multiplier/divider have been verified by showing its implementation as amplitude modulator and frequency doubler. Further, the robustness of the proposed circuit against process, voltage and temperature parameters has been observed by performing Monte Carlo, corner, temperature and PVT (process–voltage–temperature) analyses.