A new SPICE macro model of single electron transistor for efficient simulation of single-electronics circuits

To explore single-electron circuits for different applications, a proper simulation platform where circuits consisting of single electron transistors and other devices can be simulated efficiently is needed. A macro model of single electron transistor featuring symmetric tunnel junctions is proposed. In the proposed model, a voltage controlled current source is incorporated in the existing model of SET to get more accurate results. Three scaling factors have been included in the model to improve the versatility of the model. The advantages and disadvantages of different simulation methods are discussed as a justification for choosing the macro model approach. The proposed model can efficiently describe the physical phenomena occurring in coulomb blockade and coulomb oscillation regions. The SPICE environment is used for the simulation and to verify the accuracy, the model is applied to a single electron inverter circuit and the effect of macro model parameters on the noise margin is investigated to estimate the robustness of the inverter cell. A multi peak negative differential resistance circuit based on the proposed macro model is designed and demonstrated. Also, an integrator circuit has been designed to prove the validity of the proposed model in the analog domain. Further, the linearity of the integrator circuit is analyzed through harmonic and intermodulation distortion analysis.