InGaAs-Si Double Pocket-Dual Gate Tunnel FET Based 7T SRAM Design

Tunnel FETs (TFETs) are preferable over MOSFETs at lower technology nodes due to their superior performance in the subthreshold region in terms of extremely low off current and low subthreshold swing. However, limitations like low drive current, ambipolarity and unidirectional conductivity hamper the usage of TFET device in designing memory structures such as SRAM. In this paper, a new TFET device called Indium Gallium Arsenide - Silicon Double Pocket Dual Gate TFET (InGaAs-Si DP-DGTFET) is proposed. The proposed design shows a relatively high drive current, ON to OFF current ratio, ON current to gate capacitance ratio, subthreshold swing (SS), and lower threshold voltage. The 7T SRAM cell designed using the proposed TFET device significantly improves the performance in terms of read and write speed when compared to Si-DP-DGTFET based SRAM at a supply voltage of 0.7V. The proposed 7T SRAM cell also includes a TFET based NDR sense amplifier circuit to enhance the read operation for lower power consumption. This makes the proposed device a preferred choice for the application that demands high speed and stability with considerable power loss.