Power consumption reduction in systems on Chip (SoCs)Réduction de la Consommation de Puissance dans les Systèmes sur Puces

Systems on Chip are becoming extremely complex integrated circuits, containing tens or hundreds of analog,rf and digital blocks. For most applications, they have to present extremely low power consumption. It is the case, for instance, in ad hoc networks for which 100 or 1000 SoC nodes have to sense their environment, do some processing and send by radio some information to adjacent nodes in a multi-hop fashion to reach finally a base station. The design of such SoC nodes, to achieve the required extremely low power consumption, has to performed first at the system level, including low power communication protocols and data routing through the network, node wake-up strategies, low-power software and operating systems, innovative solutions for the sensor part, flexible or reconfigurable and very low power digital processing, low-power networks on chip for the communication between embedded processors and memories, as well as low powerrf front-ends. In addition, due to the impressive technology pace, new problems have to be solved for the design of SoCs, such as the interconnect delays, reliability and the dramatic increase of the static power. Some techniques, considered as the most efficient, of dynamic as well as static power reduction are described. It is however shown that the design of SoCs in 130 nm and below will impact dramatically the design methodologies, mainly due the static power increase. Finally, if today most SoCs are powered by batteries, alternative sources of energy are reviewed.