Novel optimized low power design of single-precision floating-point adder using Quantum-dot Cellular Automata

As the fabrication technology goes beyond nano-scale, the VLSI layout design using Complementary Metal Oxide Semiconductor (CMOS) becomes obsolete due to its short channel effects and leakage currents. Quantum-dot Cellular Automata (QCA) is a novel paradigm proposed to overcome the drawbacks of CMOS circuits at nano-scale. Complex arithmetical operations need accurate and fast computing architectures. Though performing arithmetical operations on fixed-point numbers is easy, however, floating-point numbers have significant advantages. Moreover, the operations on floating-point numbers decide the speed and accuracy of the arithmetic unit. Hence, it is crucial to design a precise computing architecture for floating-point numbers. This paper presents for the first time an optimized architecture using QCA technology for the addition of single-precision floating-point numbers. The proposed model has been designed with lesser number of blocks which have been proved to be the best among the existing models. The proposed floating-point adder is simulated using QCADesigner tool that requires 10,370 quantum cells in an area of 21.25 μm2 with a delay of 15 clock cycles. The energy dissipation analysis of proposed architecture is studied using QCA Designer-E tool based on which the power dissipation is also calculated. The proposed model has a power dissipation of 6.56 nW, which is an improvement of 98% compared to present CMOS technology.