Dynamic Scheduling for Heterogeneous Multicores

被引:0
|
作者
Vazquez R. [1 ]
Edun A. [1 ]
Gordon-Ross A. [1 ,2 ]
Stitt G. [1 ,2 ]
机构
[1] Department of Electrical and Computer Engineering, Univeristy of Florida, Gainesville, FL
[2] NSF Center for Space, High-Performance, and Resilient Computing (SHREC) at University of Florida, Gainesville, FL
基金
美国国家科学基金会;
关键词
Configurable caches; Dynamic scheduling; Embedded systems; Heterogeneous systems; Machine learning;
D O I
10.1007/s42979-021-00909-w
中图分类号
学科分类号
摘要
Heterogeneous multicore systems can help adherence to design goals by providing a diverse set of hardware components to meet application requirements. Each core may also have tunable hardware that can reconfigured for different applications. However, scheduling becomes difficult in the presence of tunable hardware due to the additional constraint that an application must be scheduled to a core that offers the best configuration, based on the application’s requirements, to maximize the benefit of the tunable hardware. The scheduling decision can be made by exploring and evaluating each hardware configuration in the design space exhaustively or through the use of a heuristic to evaluate a subset of the design space. However, exhaustive and heuristic approaches do not scale well with the number of available hardware configurations. To improve upon exhaustive and heuristic approaches, in this paper, we present a dynamic scheduling methodology that uses machine learning to schedule applications to the application’s respective best core for reduced energy consumption for a system with configurable caches. We use an artificial neural network (ANN) to train our predictive model, using hardware counters, to predict the best core and a tuning heuristic to determine best configuration on non-best cores. If the best core is busy, our scheduler considers alternative idle cores, or the application is stalled depending on which decision is energy advantageous. Our experiments show that our proposed system can achieve a total energy savings of approximately 33% and 2.5% compared to a fixed-cache, base system when using a configurable instruction and data cache, respectively, while remaining competitive and exhibiting better scaling properties compared to systems adopting a heuristic approach. © 2021, The Author(s), under exclusive licence to Springer Nature Singapore Pte Ltd.
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