Performance analysis of Vedic mathematics algorithms on re-configurable hardware platform

For the overall performance of systems like microprocessors and digital signal processors (DSPs) platforms, arithmetic units, all must be efficient in terms of speed, power, and area. Multipliers and dividers are inevitable hardware employed in such systems. This paper focuses on Vedic mathematics algorithms for multiplication and division for power-efficient, faster, and area-efficient design. For four- and eight-bit Vedic multiplication algorithms, Urdhva Tiryagbhyam and Nikhilam Sutras are employed in this paper. For eight-bit Vedic division algorithms, Nikhilam and Dhwajank Sutras are used. The Vedic mathematics algorithms are also compared to conventional methods of multiplication (like Array multiplier) and division (using Booth multiplication algorithm). As an application of DSP, the linear convolution operation is implemented using both conventional and Vedic algorithms. It has been observed that the Vedic algorithms operate faster, consume less power, and occupy less area on a targeted hardware platform. The implementations were carried out using the Verilog HDL language and Xilinx’s Vivado EDA tool. To measure various performance parameters, Cadence simvision (using 180-nm GPDK CMOS Technology) and Xilinx’s ISE tool were also used.