Application mapping in hybrid photonic networks-on-chip for reducing insertion loss

In this paper, the influence of the mapping algorithm on the physical layer parameters and photonic network-on-chip performance is demonstrated. Four mapping algorithms, namely hop count, congestion, no-turn, and turn, have been suggested. The proposed mapping algorithms illustrate the impact of hop count, congestion, moving in the direct and indirect paths of the insertion loss, and energy dissipation. In the proposed plan, the random mapping algorithm in the worst case was compared to that in the best case, and the four provided mapping algorithms were compared with each other in terms of the insertion loss. According to the obtained results, the turn mapping algorithm in a mesh topology using gyrokinetic toroidal code in the worst case, random mapping algorithm in the best case, and no-turn mapping algorithm were improved by 75, 70, and 9.5%, respectively. The simulation results indicate that the proposed mapping algorithms reduce the energy dissipation and insertion loss compared to the random mapping algorithm.