A family of fully integrated CMOS chaos generators with strictly 1-D linear-piecewise chaos maps

A family of three complementary metal-oxide semiconductor (CMOS) chaos generators is presented. The proposed scheme starts by obtaining strictly 1-D piecewise-linear chaos maps using a stroboscopic sampling method. The chaotic behavior is then analyzed with the help of numerical simulations using Mathematica. As required for practical applications, the robustness of the derived chaos maps was also confirmed by analyzing bifurcation and Lyapunov exponent diagrams. For verification, a tent-shape chaos generator was implemented using the 0.18-μ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu $$\end{document}m CMOS process. The simulation as well as measurement results confirmed the proposed scheme. The key advantages of the proposed chaos generators with varied fabrication parameters, including compact size, low power consumption, simple achievement of chaos, and robust chaos generation, recommend them as a solution in design of fully integrated chaotic circuits for applications where noise-like signal sources are required.