FinFET based ultra-low power 3T GC-eDRAM with very high retention time in sub-22 nm

This paper presents an ultra-low power 3T gain-cell embedded DRAM (GC-eDRAM) cell in fin field-effect transistor (FinFET). This memory structure uses fast and low leakage FinFET transistors to improve frequent refresh issue and reduce retention power consumption. To achieve high retention time and low leakage power, we use series low power transistors in the path of data failure reducing the leakage current thanks to the stack effect. Due to the slower failure of data ‘1’ and ‘0’, data retention time (DRT) and thus refresh frequency improving, refresh power and retention power reduction would be achieved. The 2-kB array was simulated in FinFET sub-22 nm process nodes using HSPICE. The proposed structure at 20 nm FinFET technology demonstrates over 130× higher DRT, 70% lower static power consumption, and over 50% lower cell area than the 4T cell in 28 nm fully-depleted silicon-on-insulator (FD-SOI) technology. Additionally, it offers three orders of magnitude reduction in retention power consumption compared to 4T DRM and 4TSS cells. The proposed 3T cell provides 100–1000× higher DRT than the 4TSS cell in FinFET sub-22 nm technologies.