Digital multiplier-less implementation of a memcapacitor and its application in chaotic oscillator

In this paper, for the first time, the FPGA-based digital emulator of the memcapacitor is proposed. This emulator can generate the pinched charge–voltage hysteresis loop of the memcapacitor. Also, by increasing the input frequency of the emulator, the area enclosed inside the hysteresis lobes shrinks, which is the main fingerprint of the memcapacitor. To simplify the hardware implementation of the memcapacitor emulator, and to reduce the implementation cost, besides using shift operations instead of multiplication operations, the multiple state memcapacitor model is introduced in which the number of possible values for the memcapacitance is limited. The proposed digital memcapacitor model is synthesized with Xilinx Synthesis Tool and implemented on the XILINX SPARTAN-6 XC6SLX9. Implementation results are consistent with simulation results from MATLAB. To evaluate the application of the proposed digital emulator, the proposed memcapacitor digital emulator is used in a chaotic circuit for generating chaotic attractors and then is verified experimentally. The experimental results show good agreement with the MATLAB simulation results. Results show that digital memcapacitor-based chaotic circuit is low cost and high speed compared to previous works, because of removing multiplication terms.