A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits with Dynamic and Static C-elements

The fast growing in complexity of digital VLSI circuits with the advance of deep sub-micron scaling causes occurrence of faults during normal operation of the circuits. These faults cannot be detected by off-line test or Built-In-Self-Test (BIST) techniques. Further, a number of critical faults may require detection at the functional mode during run-time. On-line Testing (OLT) provides a solution to both the problems, and can be implemented using appropriate Design-for-Testability (DFT) techniques. Nowadays, use of asynchronous circuits in semiconductor industry has rapidly increased because of no clock skew problem, low power consumption, average case performances and high degree of modularity. It has been found in the literature of OLT of VLSI circuits that the number of OLT schemes proposed for asynchronous circuits is very few compared to synchronous circuits. The main drawbacks of the existing OLT schemes for asynchronous circuits are protocol dependency, high area overhead and scalability. In this work, we have proposed a partial replication based OLT scheme for asynchronous circuits with dynamic and static C-elements using Binary Decision Diagram (BDD). The proposed scheme works for all circuits irrespective of their design protocols and achieves high fault coverage and comparatively low area overhead. It has been observed that the area overhead is further reduced with increase in values of FD-transitions (Fault Detecting transitions) exclusion. Furthermore, the use of BDD enables the scheme to handle fairly large circuits.