Block-Pipelining Cache for Motion Compensation in High Definition H.264/AVC Video Decoder

被引：0
|
作者：
Chen, Xianmin [1 ]
Liu, Peilin [1 ]
Zhu, Jiayi [1 ]
Zhou, Dajiang [2 ]
Goto, Satoshi [2 ]
机构：
[1] Shanghai Jiao Tong Univ, Dept Elect Engn, Shanghai 200030, Peoples R China
[2] Waseda Univ, Grad Sch Informat Prod & Syst, Kitakyushu, Fukuoka, Japan
来源：
ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5 | 2009年
关键词：
D O I：
暂无
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
In this paper, we present a cache scheme targeting hardware implementation to reduce the bandwidth of motion compensation, and a block-pipelining strategy to hide long latency of the external memory in high definition H.264/AVC video decoder. Hardware architecture is also implemented for the proposed algorithms. Experimental results show that the cache succeeds in reducing external memory bandwidth of motion compensation by 66%similar to 78% and the block-pipelining strategy can solve the latency problem better than previous solutions. Our proposed hardware architecture can averagely process one macroblock within 297 cycles, capable of real-time processing 1920x1088@30fps H.264 sequence at lower than 80MHz.
引用
收藏
页码：1069 / +
页数：2
相关论文
共 50 条
  • [1] Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder
    Zhou, Jinjia
    Zhou, Dajiang
    He, Gang
    Goto, Satoshi
    [J]. IEICE TRANSACTIONS ON ELECTRONICS, 2011, E94C (04): : 439 - 447
  • [2] Cache organizations for H.264/AVC motion compensation
    Kim, Ju-Hyun
    Hyun, Gyoung-Hwan
    Lee, Hyuk-Jae
    [J]. 13TH IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS, PROCEEDINGS, 2007, : 534 - +
  • [3] Cache Optimization for H.264/AVC Motion Compensation
    Yoon, Sangyong
    Chae, Soo-Ik
    [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2008, E91D (12): : 2902 - 2905
  • [4] Memory cache based motion compensation architecture for HDTV H.264/AVC decoder
    Li, Yu
    Qu, Yanmei
    He, Yun
    [J]. 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 2906 - 2909
  • [5] Architecture design of H.264/AVC decoder with hybrid task pipelining for high definition videos
    Chen, TW
    Huang, YW
    Chen, TC
    Chen, YH
    Tsai, CY
    Chen, LG
    [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 2931 - 2934
  • [6] A new motion compensation design for H.264/AVC decoder
    Wang, SZ
    Lin, TA
    Liu, NM
    Lee, CY
    [J]. 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 4558 - 4561
  • [7] Complexity modeling for motion compensation in H.264/AVC decoder
    Lee, Szu-Wei
    Kuo, C. -C. Jay
    [J]. 2007 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOLS 1-7, 2007, : 2565 - +
  • [8] Bus bandwidth aware H.264/AVC motion compensation design for high definition video encoding
    Park, Chan-Sik
    Kim, Ju-Hee
    [J]. 2007 IEEE NINTH WORKSHOP ON MULTIMEDIA SIGNAL PROCESSING, 2007, : 276 - 279
  • [9] An adaptive pipelining scheme for H.264/AVC CABAC decoder
    陈杰
    Ding Dandan
    Yu Lu
    [J]. High Technology Letters, 2013, 19 (04) : 391 - 397
  • [10] Motion compensation sample processing for HDTV H.264/AVC decoder
    Azevedo, Arnaldo
    Zatt, Bruno
    Agostini, Luciano
    Bampi, Sergio
    [J]. NORCHIP 2005, PROCEEDINGS, 2005, : 110 - 113
12345