Instrumentation design for gate and drain low frequency noise measurements

被引：19

作者：

Giusi, G. ^{[1
]}

Crupi, F. ^{[2
]}

Ciofi, C. ^{[1
]}

Pace, C. ^{[2
]}

机构：

[1] Univ Messina, DFMTFA, INFM, Salita Sperone 31, I-98166 Messina, Italy

[2] Univ Calabria, DEIS, I-87030 Arcavacata Di Rende, Italy

来源：

2006 IEEE INSTRUMENTATION AND MEASUREMENT TECHNOLOGY CONFERENCE PROCEEDINGS, VOLS 1-5 | 2006年

关键词：

low noise amplifiers; low frequency noise; CMOS devices; drain noise; gate noise;

D O I：

10.1109/IMTC.2006.328224

中图分类号：

TH7 [仪器、仪表];

学科分类号：

0804 ; 080401 ; 081102 ;

摘要：

In this paper we present an on-wafer measurement system suited for the characterization of low frequency current noise in CMOS devices. Guidelines for designing the preamplifier and the bias stage at the drain and gate terminals are discussed. A simple implementation of the proposed design approach is reported. The system capability is tested through 1/f noise measurements in advanced CMOS devices.

引用

页码：1747 / +

页数：2

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