Hardware design for modern radar processing

被引:4
|
作者
Bierens, LHJ [1 ]
机构
[1] TNO, Phys & Elect Lab, NL-2509 JG The Hague, Netherlands
来源
关键词
D O I
10.1049/ecej:19970604
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Programmability and flexibility are often emphasised in today's hardware design for modern radar processing, but in many radar applications this does not lead to the desired optimum hardware solution, especially if application-specific requirements, such as limited processor size and power consumption combined with extremely high throughputs, play a key role. Many parts of a radar processing system can be optimised if dedicated hardware solutions are permitted for the so-called 'bulk-processing', which requires a low degree of flexibility and has a high algorithmic regularity. In this paper some arguments are given in favour of combined programmable/dedicated-hardware solutions for radar processing applications, supported by illustrative application and design examples.
引用
收藏
页码:257 / 270
页数:14
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