Metrology at the Leading Edge

The challenges facing characterization and metrology of future semiconductor technology is described in the 2005 ITRS Metrology Roadmap[1]. These challenges are driven by the technologies for future device structures that include molecular electronics, spintronics, nanotube and nanowire based electronics, and other futuristic concepts. Although the challenges are separated into the pre and post 32 nm 1/2 pitch nodes, these challenges represent the issues facing the extension of CMOS for another 15 years. Additional challenges are described in a section covering measurement needs for technology beyond CMOS. In this presentation, a brief overview of measurement issues will be described for both CMOS extension and beyond CMOS electronics.