A Design of Ultra-Low Power Low-Dropout Regulator for DSRC system

被引：0
|
作者：
Oh, Su-Jin [1 ]
Ahn, Yong-Deok [1 ]
Kim, Sung-Jin [1 ]
Lee, Kang-Yoon [1 ]
机构：
[1] Sungkyunkwan Univ, Dept Elect & Comp Engn, Seoul, South Korea
来源：
2019 34TH INTERNATIONAL TECHNICAL CONFERENCE ON CIRCUITS/SYSTEMS, COMPUTERS AND COMMUNICATIONS (ITC-CSCC 2019) | 2019年
关键词：
Ultra-Low Power LDO; Always-on domain; SPI management;
D O I：
暂无
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
In this paper, we describe Ultra-Low Power (ULP) Low-Dropout Regulator (LDO) circuits for SPI module management in DSRC system. So LDO is Always-On domain. Circuit uses a CMOS 18 nm process. Proposed ULP LDO's output voltage and input voltage is 3.3 V and 1.2 V and total current consumption is 66 nA. By using 2-Transistor voltage reference circuit, Error Amplifier.
引用
收藏
页码：371 / 372
页数：2
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