On-chip transimpedance preamplifier for CMOS BDJ optical detector using active enhanced impedance loads

A novel self-bias transimpedance preamplifier is proposed to be integrated on the same chip with a CMOS BDJ (Buried Double p-n Junction) optical detector. This preamplifier is built with an input bias stage driving three transimpedance active loads. Its three output signals are respectively proportional to the detector's photocurrents I-1, I-2 and (I-1 + I-2). These signals are needed for the detector to be operated either as a wavelength-sensitive detector and as a photo-detector. The proposed circuitry is designed in a double-poly 0.8-mum CMOS technology, with no requirement for external component. It provides high transimpedance thanks to the use of regulated cascode transistors and implementation of bias-stabilization technique. Transistor-level simulations show a do transimpedance of 4GOmega and a cutoff frequency of 18Hz.